According to the known art, MIM integration utilizes a separate mask to define each MIM plate, i.e., two (2) masks for a single MIM and three (3) masks for a dual MIM in all Cu BEOL Integration. For the aluminum MIM version, the bottom plate is formed of the same material as the wiring level so that an extra mask is needed only for the top plate in single MIM or for the top and middle plates in dual MIM.
For higher capacitance, more mask levels are required, which makes the MIM more expensive. After HiK, super high capacitance MIMs will only be possible with more MIM levels. Thus, there is a need for cheaper integration in order to increase MIM levels without adding further masking levels.
A conventional process for dual MIM integration is shown in FIGS. 1-5. A capacitor 100 to be formed is shown having a conductive top plate 101, e.g., titanium nitride (TiN), a first dielectric layer 102, e.g., silicon dioxide (SiO2), SiN, Hi-K materials, a conductive second plate 103, e.g., TiN, a second dielectric layer 104, e.g., SiO2, SiN, Hi-K materials, and a conductive bottom plate 105. Bottom plate 105, which may be a sandwiched conductor of more than one metal, e.g., titanium nitride/tungsten/titanium nitride (TiN/W/TiN), is formed on an insulating layer 106, e.g., SiO2, acting as an etch stop layer, which is formed on insulating layer 107, e.g., silicon nitride, acting as a diffusion barrier from conductors 108, e.g., copper.
In a second step, depicted in FIG. 2, in the formation of capacitor 100, a resist 110, formed of a resist material suitable for the etching to be performed, is placed over top plate 101. Portions of plate 101 lying outside of mask 101 are removed, e.g., via etching, to first dielectric layer 102. In a third step in the process, shown in FIG. 3, a second mask 120, is placed over upper layer 101, i.e., to envelop the entire layer, and onto first dielectric layer 102 to define the geometry of second plate 103. The portions of first dielectric layer 102 and second plate 103 outside of mask 120 are removed to second dielectric layer 104. In a fourth step in the process, shown in FIG. 4, a third mask 130 is placed over upper layer 101, first dielectric layer 102, and second layer 103, i.e., to envelop the entireties of these layers, and onto second dielectric layer 104 to define the geometry of bottom plate 105. The portions of second dielectric layer 104 and bottom plate 105 outside of mask 130 are removed to etch stop layer 106. In the fifth step shown in FIG. 5, the dual MIM parallel wiring is coupled from conductor 112 to capacitor 100 through vias 114, 115, 116, and 117, e.g., copper, and from conductor 113 to capacitor 100 through via 118, e.g., copper.